library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demJonhson is
port(
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC_vector(7 downto 0)
);
end demJonhson;
--}} End of automatically maintained section
architecture demJonhson of demJonhson is
begin
process(CLK,RST)
variable x:integer range 0 to 15;
begin
if RST='1' then
x:=0;
else
if CLK'event and CLK ='1'then
if x=15 then
x:=0;
else
x:=x+1;
end if;
end if;
end if;
case x is
when 0 => Q<= "00000000";
when 1 => Q<= "00000001";
when 2 => Q<= "00000011";
when 3 => Q<= "00000111";
when 4 => Q<= "00001111";
when 5 => Q<= "00011111";
when 6 => Q<= "00111111";
when 7 => Q<= "01111111";
when 8 => Q<= "11111111";
when 9 => Q<= "11111110";
when 10 => Q<="11111100";
when 11 => Q<="11111000";
when 12 => Q<="11110000";
when 13=> Q<= "11100000";
when 14 => Q<="11000000";
when 15 => Q<="10000000";
end case;
end process;
-- enter your statements here --
end demJonhson;
